1. Field of the Invention
The invention relates to an I2C bus control circuit that enables reduction in transmission time by efficiently using an I2C bus that is used for an interface between internal devices such as electronic equipments.
2. Background Art
I2C bus control needs to conform to the Philips I2C specification (see THE I2C-BUS SPECIFICATION VERSION 2.1, JANUARY 2000). This specification does not designate a method for implementing I2C bus control, but there are various methods for implementing I2C bus control.
Conventionally, an I2C bus control circuit connected to a controller usually processes data on a byte-by-byte basis. More specifically, a conventional I2C bus control circuit is connected to a controller for conducting controlling and monitoring operations. When the controller sets 1-byte transmission data to the I2C bus control circuit, the I2C bus control circuit transmits 1-byte data and then outputs an interrupt signal to the controller. The controller sets the next transmission data to the I2C bus control circuit in response to the interrupt signal. A plurality of continuous data signals are transmitted by repeating this operation.
FIG. 1 shows the structure of a conventional I2C bus control circuit 110 and a controller 119 connected to the I2C bus control circuit 110 for conducting monitoring and controlling operations. The I2C bus control circuit 110 includes a data line control section 111, a clock line control section 112, a transmission control section 113, and a sequence control section 116. The data line control section 111 is connected to a data line (SDA) of an I2C bus 123. The clock line control section 112 is connected to a clock line (SCL) of the I2C bus 123. The transmission control section 113 controls transmission according to the setting by the controller 119. The sequence control section 116 conducts status management, error detection, timing control, and the like. The transmission control section 113 has a transmission data register 114 and a parallel-to-serial conversion section 115. The sequence control section 116 has an arbitration section 117 and an error detection section 118. FIG. 2 shows the structure of the transmission data register 114 of the transmission control section 113.
The I2C bus control circuit 110 of FIG. 1 conducts data transmission as follows: data is set to the transmission data register 114 of the transmission control section 113. In synchronization with the timing generated by the sequence control section 116, the parallel-to-serial conversion section 115 converts the data in the transmission data register 114 of the transmission control section 113 and transmits the resultant data to the data line control section 111. The data line control section 111 and the clock line control section 112 respectively control the data line (SDA) and the clock line (SCL) in synchronization with the timing generated by the sequence control section 116.
The controller 119 includes a ROM (read only memory) 120 and a RAM (random access memory) 121. A program for controlling the I2C bus control circuit 110 is stored in the ROM 120 and data to be used during execution of the program is stored in the RAM 121. The controller 119 controls the I2C bus control circuit 110 by executing the program stored in the ROM 120 to transmit a plurality of continuous data signals.
Hereinafter, a processing flow of the program will be described.
STEP 1: A plurality of continuous transmission data signals and the number of transmission data signals are stored in the RAM 121. The program is terminated when the number of transmission data signals is zero.
STEP 2: The first byte of the plurality of continuous transmission data signals and a START condition control bit (a STOP condition control bit is not set) is set to the transmission data register 114 according to the configuration of the transmission data register 114 of the transmission control section 113, and the number of transmission data signals in the RAM 121 is decremented by one.
STEP 3: The START condition and the 1-byte data are transmitted in the I2C bus control circuit 110. After the transmission is completed, an interrupt signal 122 is transmitted from the sequence control section 116 of the I2C bus control circuit 110 to the controller 119. In the case where the number of transmission data signals in the RAM 121 is one or more, the next byte of the plurality of continuous transmission data signals (a START condition control bit and a STOP condition control bit are not set) is set to the transmission data register 114, and the number of transmission data signals in the RAM 121 is decremented by one. In the case where the number of transmission data signals in the RAM 121 is zero, a STOP condition control bit (a START condition control bit and transmission data are not set) is set to the transmission data register 114 and the I2C bus control circuit 110 transmits the STOP condition.
STEP 4: The 1-byte data is transmitted in the I2C bus control circuit 110. After the transmission is completed, an interrupt signal 122 is transmitted from the sequence control section 116 of the I2C bus control circuit 110 to the controller 119. In the case where the number of transmission data signals in the RAM 121 is one or more, the next byte of the plurality of continuous transmission data signals (a START condition control bit and a STOP condition control bit are not set) is set to the transmission data register 114, and the number of transmission data signals in the RAM 121 is decremented by one. In the case where the number of transmission data signals in the RAM 121 is zero, a STOP condition control bit (a START condition control bit and transmission data are not set) is set to the transmission data register 114 and the I2C bus control circuit 110 transmits the STOP condition.
STEP 5: Step 4 is repeated.
Transmission of a plurality of continuous data signals is thus implemented by the conventional I2C bus control circuit 110. FIG. 3 is an example of waveforms on the I2C bus 123 obtained when a plurality of continuous data signals are transmitted by the conventional I2C bus control circuit 110.
In the example of FIG. 1, the I2C bus control circuit 110 and the controller 119 are provided as separate devices and connected to each other. However, there are examples in which the I2C bus control circuit 110 and the controller 119 are provided in the same device as a microcontroller 1010 including an I2C bus control circuit.
As has been described above, transmission of a plurality of continuous data signals is implemented by the conventional I2C bus control circuit 110 connected to and controlled by the controller 119. In this structure, the timing of setting transmission data is implemented by an interrupt signal 122 from the I2C bus control circuit 110. The transmission time of a plurality of continuous data signals not only depends on the clock cycle of the I2C bus 123 but includes overhead of the interrupt processing of the controller 119. In other words, the time corresponding to a product of the overhead of the interrupt processing of the controller 119 and the number of transmission bytes is wasted.
Moreover, the I2C bus specification has been extended in recent years, enabling high speed communication. Therefore, the impact of the interrupt processing overhead has been increasing.
Furthermore, improved functionality of electronic equipments such as AV (audio visual) equipments has increased the amount of communication on the I2C bus in the equipments, which affects performance of the electronic equipments. For example, in the case where the channel is switched on a television, data corresponding to a video processing device, a sound processing device, and the like is usually transmitted all at once according to a video format and a sound format of the switched channel, and video mute and sound mute are ON during transmission of the data so that no distorted video and sound are output. If the transmission time is long, video mute and sound mute are kept ON for a long time, which bothers the viewers.